1. Field of the Invention
The present invention relates to a process of fabricating a capacitor, and more particularly to a method of fabricating a capacitor over bit line and a bottom electrode thereof.
2. Description of Related Art
Semiconductor memory devices, for example, dynamic random access memory (DRAM), normally require a capacitor so that a binary data can be stored in a memory cell according to the bias voltage provided by the capacitor. The electric charges stored in the capacitor are the basic characteristic of the DRAM. The quantity of electric charges stored in the capacitor depends on its capacitance, and the capacitance of a capacitor depends on the area of the storage electrodes, the reliability of the insulation between the top and bottom electrodes and the dielectric constant of the dielectric material.
FIGS. 1-1 through 5-3 are schematic top views showing the process for fabricating a capacitor-terminal contact of a conventional capacitor over bit line. The complex process of fabricating the capacitor according to a prior art may be briefly described as follows.
FIG. 1-2 is a schematic cross-sectional view along the line II-II of FIG. 1-1 and FIG. 1-3 is a schematic cross-sectional view along the line III-III′ of FIG. 1-1. As shown in FIGS. 1-1, 1-2 and 1-3, an active region 102 is defined in the substrate 100 and an isolation region 104 is formed around the active region 102 before the capacitor over bit line is fabricated. In FIG. 1-1, the dash lines indicate the active region 102. Next, a plurality of word lines 106 running across the active region 102 is formed on the substrate 100. Next, a landing plug contact (LPC) 108 is formed on the active region 102 between each word line 106 and landing plug contact (LPC) 108 is formed on a portion of the isolation region 104. A dielectric layer 110 is formed to cover the remaining portion of the substrate 100. Thereafter, a second dielectric layer 112 is formed over the entire surface of the structure and then a bit line contact opening 114 that exposes a portion of the LPC 108 is formed in the second dielectric layer 112.
Next, as shown in FIGS. 2-1, 2-2 (cross-sectional view along the line II-II of FIG. 2-1) and 2-3 (cross-sectional view along the line III-III′ of FIG. 2-1), a bit line 116 is formed on the second dielectric layer 112. The bit line 116 passes through the bit line contact opening 114 and is electrically connected to the landing plug contact 108. Although only a single diagram is used to show the formation of the bit line 116, the process of forming of this bit line 116 at least includes sequentially depositing a barrier metal layer 118, a titanium nitride adhesive layer 120, a metal layer 122, a bit line hard mask layer 124, etching bit line hard mask layer 124, the metal layer 122, the titanium nitride adhesive layer 120 and the barrier metal layer 118 respectively, and forming spacers 126 on the sidewalls of the entire etched structure. Thus, several process steps are required for forming the bit line 116.
Next, as shown in FIGS. 3-1 (cross-sectional view along the line II-II of FIG. 2-1) and 3-2 (cross-sectional view along the line III-III′ of FIG. 2-1), a phosphosilicate glass (PSG) layer 128 is deposited over the substrate 100 to cover the bit line 116. Next, an oxide layer 130 is formed over the PSG layer using tetra-ethyl-ortho-silicate (TEOS) as the gaseous source in the deposition.
As shown in FIGS. 4-1, 4-2 (cross-sectional view along the line II-II of FIG. 4-1) and 4-3 (cross-sectional view along the line III-III′ of FIG. 4-1), the deposited layers (for example, 128 and 130) on the surface of FIG. 4-1 are omitted to provide a better view of the locations of various underlying components. To form several capacitor-terminal contacts, a polysilicon hard mask layer 132 is formed on the oxide layer 130. Next, an etching process is performed using the layer 132 as an etching mask to form a plurality of capacitor-terminal contact openings 134 that exposing portions the landing plug contacts 108.
As shown in FIGS. 5-1, 5-2 (cross-sectional view along the line II-II of FIG. 5-1) and 5-3 (cross-sectional view along the line III-III′ of FIG. 5-1), the deposited layers (for example, 128 and 130) on the surface of FIG. 5-1 are omitted to provide a better view of the locations of various underlying components. After forming the capacitor-terminal contact openings 134, the polysilicon hard mask layer 132 is removed. Thereafter, conductive material is deposited in the capacitor-terminal contact openings 134 to form a plurality of capacitor-terminal contacts 136 electrically connected to the respective landing plug contacts 108.
However, according to the foregoing description of the method of fabricating the capacitor-terminal contacts, several complicated processing steps for forming the capacitor. Therefore, a simplified process for fabricating the capacitor is highly desirable.